To test these new chips efficiently, chipmakers will have to look to system level test (SLT) to complement conventional methods.
That's because SLT overcomes the limitations of conventional test methods. These include rising levels of untested transistors at each new node, increasing chip complexities and demanding test paradigms.
In a Tuesday report, analyst Lai Gene Lih says, “We believe currently nascent adoption could accelerate as chipmakers increasingly see SLT as a necessity to either reduce cost of test (CoT) or avoid large liabilities as a result of product failure, such as product recalls.”
However, for SLT to reduce cost of test (CoT), the implementation should be massively parallel, asynchronous, and highly customisable to customer needs.
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Fortunately, these features are the strength of AEM’s HDMT and AMPS test handlers.
With this, Lai believes the shift in industry dynamics could promote customer stickiness with core customers, while opening up opportunities with potential customers. But the group may face competitive pressures from the products of new competitors and consolidation by adjacent players.
“AEM appears well positioned given its early mover advantage and strong know-how. AEM may even be an M&A target, given attractive valuation of 6 times FY19E EV/EBITDA,” says Lai.
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Depending on the profile of the acquirer, synergies could stem from horizontal integration to improve product proposition, or from gaining access to a global client base.
As at 11.50am, shares in AEM Holdings are trading 1.94% higher at $1.05, translating to a FY19F price-to-book ratio of 2.5 with a dividend yield of 2.5%.
